april 2001 . revision 1.0 1/9 more than 3 pci masters with stpc client by m. zoppi and m. tabet AN1081 application note 1. overview. this document provides detailed information regarding the way to implement a pal device that will allow an stpc client motherboard to support more than 3 pci master devices. this document is intended to support the following device: stpc client for additional information on the stpc client specifications, please refer to the stpc client databook. information in this document is subject to change without notification. stmicroelectronics values your feedback. please send it and any recommendations you may have regarding this document to stpc.support@st.com with the subject line AN1081. 2. background. the stpc client implements the internal logic to handle up to 3 pci master devices. that means that stpc client support 3 pcireq# and 3 pcignt# signals. the pal described here below is intended to handle more than 3 pci master devices in a design using the stpc client. as one pal is capable to manage up to 4 pci master devices, up to 12 masters can be connected to the stpc client. 2.1 description. the four req# signal from the master devices are connected to the pal that generates just one req# to the stpc client. then the stpc generates the gnt# signal that is forwarded to the requesting master. the pal 'remembers' the last master served in order to avoid to always serve first the same master, when two or more requests are pending simultaneously. the device used is a 22v10-10. 2.2k pull-up resistors are needed for the four input master requests and for the stpc client req# signal.
2/9 revision 1.0 april 2001 application note all other pins not mentioned in the following drawing must be not connected. the pal has been checked with simulation test vectors but has not been implemented on a stpc client motherboard by ourself 2.2 pinout mgnt1 mgnt2 q0 (nc) q1 (nc) q2 (nc) stpc client req (2.2k p-up) l (nc) a (nc) mgnt4 mgnt3 g n 4 3 2 1 28 27 26 v c c pciclk pcires stpc client gnt 5 6 7 8 9 10 11 12 13 14 15 16 17 18 d 24 23 22 21 20 19 25 mreq1 (2.2k p-up) mreq2 (2.2k p-up) mreq3 (2.2k p-up) mreg4 (2.2k p-up)
april 2001. revision 1.0 3/9 application note 2.3 equations and test vectors the following equations have been used to generate the jedec file able to program the pal described above: module mm1 title 'four pci masters handler for stpc client' by m. zoppi 28/5/98 stmicroelectonics 165, rue e. branly 01637 saint-genis pouilly cedex france mm1 device 'p22v10c' ; q0,q1,q2 pin 23,24,25 istype 'reg,invert'; clock pin 2 ; reset pin 3 ; r1,r2,sipg,r3,r4 pin 5,6,4,9,10 ; a, l pin 19,20 istype 'reg'; g1,g2,sipr,g3,g4 pin 26,27,21,17,18 ; sreg = [q2,q1,q0]; "state values... s = 0; b = 1; c = 2; d = 3 ; e = 4; f = 5; g = 6; k = 7 ; equations [q2,q1,q0,a,l].clk = clock; [q2,q1,q0,a,l].ar = !reset ; state_diagram sreg; state k : sipr = 1 ; a:=1 ; l:=1 ; g1 = 1 ; g2 = 1 ; g3 = 1 ; g4 = 1 ; goto s with { sipr = 1 ; a:=1 ; l:=1 ; g1 = 1 ; g2 = 1 ; g3 = 1 ; g4 = 1 ;
4/9 revision 1.0 april 2001 application note } state s: a:= a ; l:=l ; sipr = r1*r2*r3*r4 ; g1 = 1 ; g2 = 1 ; g3 = 1 ; g4 = 1 ; if (a*l*!r2) then c else if (a*l*!r3) then d else if (a*l*!r4) then e else if (a*l*!r1) then b else if (!a*l*!r3) then d else if (!a*l*!r4) then e else if (!a*l*!r1) then b else if (!a*l*!r2) then c else if (!a*!l*!r4) then e else if (!a*!l*!r1) then b else if (!a*!l*!r2) then c else if (!a*!l*!r3) then d else if (a*!l*!r1) then b else if (a*!l*!r2) then c else if (a*!l*!r3) then d else if (a*!l*!r4) then e else s with { sipr = 1 ; g1 = 1 ; g2 = 1 ; g3 = 1 ; g4 = 1 ; a:= a ; l:=l ;
april 2001. revision 1.0 5/9 application note } state b: sipr = r1*r2*r3*r4 ; g1 = sipg ; g2 = 1; g3 = 1; g4 = 1; a := 1 ; l :=1 ; if (!r1) then b with { sipr = r1*r2*r3*r4 ; g1 = sipg ; g2 = 1; g3 = 1; g4 = 1; a := 1 ; l :=1 ; } else s with { sipr = r1*r2*r3*r4 ; g1 = sipg ; g2 = 1; g3 = 1; g4 = 1; a := 1 ; l :=1 ; } state c: sipr = r1*r2*r3*r4 ; g2 = sipg ; g1 = 1; g3 = 1; g4 = 1; a := 0 ; l :=1 ; if (!r2) then c with { sipr = r1*r2*r3*r4 ; g2 = sipg ; g1 = 1; g3 = 1; g4 = 1; a := 0 ; l :=1 ; } else s with { sipr = r1*r2*r3*r4 ; g2 = sipg ; g1 = 1; g3 = 1; g4 = 1; a := 0 ; l :=1 ; } state d:
6/9 revision 1.0 april 2001 application note sipr = r1*r2*r3*r4 ; g3 = sipg ; g2 = 1; g1 = 1; g4 = 1; a := 0 ; l :=0 ; if (!r3) then d with { sipr = r1*r2*r3*r4 ; g3 = sipg ; g2 = 1; g1 = 1; g4 = 1; a := 0 ; l :=0 ; } else s with { sipr = r1*r2*r3*r4 ; g3 = sipg ; g2 = 1; g1 = 1; g4 = 1; a := 0 ; l :=0 ; } state e: sipr = r1*r2*r3*r4 ; g4 = sipg ; g2 = 1; g1 = 1; g3 = 1; a := 1 ; l :=0 ; if (!r4) then e with { sipr = r1*r2*r3*r4 ; g4 = sipg ; g2 = 1; g1 = 1; g3 = 1; a := 1 ; l :=0 ; } else s with { sipr = r1*r2*r3*r4 ; g4 = sipg ; g2 = 1; g1 = 1; g3 = 1; a := 1 ; l :=0 ; } state f : goto k ; state g :
april 2001. revision 1.0 7/9 application note goto k ; test_vectors([clock,reset,r1,r2,r3,r4,sipg]->[sreg,g1,g2,g3,g4,a,l,sip]) [ .c. , 0 , 1 , 1,1 , 1, 1 ] ->[ k ,1 , 1 ,1 , 1,0,0, 1 ]; [ .c. , 1 , 1 , 1,1 , 1, 1 ] ->[ s ,1 , 1 ,1 , 1,1,1, 1 ]; [ .c. , 1 , 1 , 0,1 , 1, 1 ] ->[ c ,1 , 1 ,1 , 1,1,1, 0 ]; [ .c. , 1 , 1 , 0,1 , 1, 1 ] ->[ c ,1 , 1 ,1 , 1,0,1, 0 ]; [ .c. , 1 , 1 , 0,1 , 0, 0 ] ->[ c ,1 , 0 ,1 , 1,0,1, 0 ]; [ .c. , 1 , 1 , 0,1 , 0, 0 ] ->[ c ,1 , 0 ,1 , 1,0,1, 0 ]; [ .c. , 1 , 1 , 0,1 , 0, 0 ] ->[ c ,1 , 0 ,1 , 1,0,1, 0 ]; [ .c. , 1 , 1 , 1,1 , 0, 0 ] ->[ s ,1 , 1 ,1 , 1,0,1, 0 ]; [ .c. , 1 , 1 , 1,1 , 0, 0 ] ->[ e ,1 , 1 ,1 , 0,0,1, 0 ]; [ .c. , 1 , 1 , 1,1 , 0, 0 ] ->[ e ,1 , 1 ,1 , 0,1,0, 0 ]; [ .c. , 1 , 1 , 1,1 , 0, 0 ] ->[ e ,1 , 1 ,1 , 0,1,0, 0 ]; [ .c. , 1 , 1 , 1,1 , 1, 0 ] ->[ s ,1 , 1 ,1 , 1,1,0, 1 ]; [ .c. , 1 , 1 , 1,1 , 1, 1 ] ->[ s ,1 , 1 ,1 , 1,1,0, 1 ]; [ .c. , 1 , 1 , 1,0 , 0, 1 ] ->[ d ,1 , 1 ,1 , 1,1,0, 0 ]; [ .c. , 1 , 1 , 1,0 , 0, 1 ] ->[ d ,1 , 1 ,1 , 1,0,0, 0 ]; [ .c. , 1 , 1 , 1,0 , 0, 0 ] ->[ d ,1 , 1 ,0 , 1,0,0, 0 ]; end. 3. technical support stmicroelectronics is on the internet with a world wide web (www) site on which product presentation, technical literature as well as product support information can be found. a dedicated stpc section is available providing up to date hardware documentation and software tools. the web and e-mail addresses are: www : http//www.st.com/products/support/stpc e-mail : stpc.support@st.com
8/9 revision 1.0 april 2001 application note
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 9 revision 1.0
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